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wedpn16m64vr-xb2x 1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 general description the 128mbyte (1gb) sdram is a high-speed cmos, dynamic random-access, memory using 4 chips containing 268,435,456 bits. each chip is internally con gured as a quad-bank dram with a synchronous interface. each of the chip?s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. the mcp also incorporates two 16-bit universal bus drivers for input control signals and addresses. read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0- 12 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. the sdram provides for programmable read or write burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the 1gb sdram uses an internal pipelined architecture to achieve high-speed operation. this architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. the 1gb sdram is designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided, along with a power-saving, power-down mode. all inputs and outputs are lvttl compatible. sdrams offer substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. 16mx64 registered synchronous dram features ? registered for enhanced performace of bus speeds ? 100, 125, 133mhz ? package: ? 219 plastic ball grid array (pbga), 25 x 25mm ? single 3.3v 0.3v power supply ? fully synchronous; all signals registered on positive edge of system clock cycle ? internal pipelined operation; column address can be changed every clock cycle ? internal banks for hiding row access/precharge ? programmable burst length 1,2,4,8 or full page ? 8,192 refresh cycles ? commercial, industrial and military temperature ranges ? organized as 16m x 64 ? user con gureable as 2 x 16m x 32 ? weight: wedpn16m64vr-xb2x - 2.5 grams typical benefits ? 51% space savings ? 17% i/o reduction ? reduced part count ? reduced trace lengths for lower parasitic capacitance ? glue-less connection to memory controller/pci bridge ? suitable for hi-reliability applications * this product is subject to change without notice.
wedpn16m64vr-xb2x 2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 figure 1 ? pin configuration note: dnu = do not use; to be left unconnected for future upgrades. nc = not connected internally. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a b c d e f g h j k l m n p r t dq 1 dq 3 dq 6 dq 7 cas# cs 0 # v ss v ss nc nc dq 56 dq 57 dq 60 dq 62 vss v ss dq 30 dq 28 dq 25 dq 24 clk 1 le# v cc v cc dnu nc dq 39 dq 38 dq 35 dq 33 v cc dq 0 dq 2 dq 4 dq 5 dqmb 0 we# ras# v ss v ss nc nc dqm b7 dq 58 dq 59 dq 61 dq 63 dq 31 dq 29 dq 27 dq 26 nc dqmb3 nc v cc v cc nc nc dqmb4 dq 37 dq 36 dq 34 dq 32 dq 14 dq 12 dq 10 dq 8 v cc v cc v cc v cc v cc v cc v cc v cc dq 55 dq 53 dq 51 dq 49 dq 17 dq 19 dq 21 dq 23 v ss v ss v ss vss v ss v ss v ss v ss dq 40 dq 42 dq 44 dq 46 dq 15 dq 13 dq 11 dq 9 dqmb1 clk 0 cke v cc v cc nc nc nc dq 54 dq 52 dq 50 dq 48 dq 16 dq 18 dq 20 dq 22 dqmb2 oe # cs 1 # v ss v ss nc clk 2 dqmb5 dq 41 dq 43 dq 45 dq 47 v ss v ss v cc v cc nc nc nc v ss v ss nc nc dqmb6 nc v ss v cc v cc v cc v cc v ss v ss nc nc nc v cc v cc nc nc nc nc v cc v ss v ss a 9 a 0 a 2 a 12 nc nc nc nc nc nc a 8 a 1 a 3 dnu nc nc nc nc nc nc a 10 a 7 a 5 dnu ba 0 nc nc nc nc nc a 11 a 6 a 4 dnu ba 1 nc nc nc nc nc v ss v ss v cc v cc nc nc nc v ss v cc v cc v cc v cc v ss v ss nc nc nc v cc v ss v ss top view
wedpn16m64vr-xb2x 3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 figure 2 ? functional block diagram clk 2 dqmb 0-7 we# cke ras# cas# cs 0-1 # dqmb 0-7 web# cke ras# cas# cs 0-1 # oe# le# oe# le# oe# we# ras# cas# a 0-12 ba 0-1 clk cke cs# dqml dqmh clk 0 cke cs 0 # dqmb 0 dqmb 1 we# ras# cas# a 0-12 ba 0-1 clk cke cs# dqml dqmh clk 0 cke cs 1 # dqmb 2 dqmb 3 we# ras# cas# a 0-12 ba 0-1 clk cke cs# dqml dqmh clk 1 cke cs 0 # dqmb 4 dqmb 5 we# ras# cas# a 0-12 ba 0-1 clk cke cs# dqml dqmh clk 1 cke cs 1 # dqmb 6 dqmb 7 we# ras# cas#
wedpn16m64vr-xb2x 4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 functional description read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0-12 select the row). the address bits (a0-8) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections provide detailed information covering device initialization, register de nition, command descriptions and device operation. initialization sdrams must be powered up and initialized in a prede ned manner. operational procedures other than those speci ed may result in unde ned operation. once power is applied to v cc and v ccq (simultaneously) and the clock is stable (stable clock is de ned as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100 s delay prior to issuing any command other than a command inhibit or a nop. starting at some point during this 100 s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 100 s delay has been satis ed with at least one command inhibit or nop command having been applied, a precharge command should be applied. all banks must be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. register definition mode register the mode register is used to de ne the speci c mode of operation of the sdram. this de nition includes the selec-tion of a burst length, a burst type, a cas latency, an operating mode and a write burst mode, as shown in figure 3. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 speci es the type of burst (sequential or interleaved), m4-m6 specify the cas latency, m7 and m8 specify the operating mode, m9 speci es the write burst mode, and m10 and m11 are reserved for future use. address a12 (m12) is unde ned but should be driven low during loading of the mode register. the mode register must be loaded when all banks are idle, and the controller must wait the speci ed time before initiating the subsequent operation. violating either of these requirements will result in unspeci ed operation. burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in figure 3. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-8 when the burst length is set to two; by a2-8 when the burst length is set to four; and by a3-8 when the burst length is set to eight. the remaining (least signi cant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 1.
wedpn16m64vr-xb2x 5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 table 1 ? burst definition figure 1 ? mode register definition notes: 1. for full-page accesses: y = 512. 2. for a burst length of two, a1-8 select the block-of-two burst; a0 selects the starting column within the block. 3. for a burst length of four, a2-8 select the block-of-four burst; a0-1 select the starting column within the block. 4. for a burst length of eight, a3-8 select the block-of-eight burst; a0-2 select the starting column within the block. 5. for a full-page burst, the full row is selected and a0-8 select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0-8 select the unique column to be accessed, and mode register bit m3 is ignored. burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 0 0-1 0-1 1 1-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0-9/8/7 (location 0-y) cn, cn + 1, cn + 2 cn + 3, cn + 4... ?cn - 1, cn? not supported 12 11 10 9 8 7 6 5 4 3 2 1 0 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a 9 a 7 a 6 a 5 a 4 a 3 a 8 a 2 a 1 a 0 mode register (mx) address bus m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a 10 a 11 a 12 reserved* unused wb 0 1 write burst mode programmed burst length single location access m9 *should program m12, m11, m10 = 0, 0 to ensure compatibility with future devices.
wedpn16m64vr-xb2x 6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the rst piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n+m. the i/os will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the i/os will start driving after t1 and the data will be valid by t2. table 2 below indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by setting m7and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses table 2 - cas latency speed allowable operating frequency (mhz) cas latency = 2 cas latency = 3 -133 100 133 -125 100 125 -100 66 100 figure 4 ? cas latency
wedpn16m64vr-xb2x 7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 commands the truth table provides a quick reference of available commands. this is followed by a written description of each command. three additional truth tables appear following the operation section; these tables provide current state/ next state information. inputs output oe# le# clk a y hxxx z llxl l llxh h lh i l l lhih h l h l or h x y 0 (1) notes: 1. output level before the indicated steady-state input conditions were established. register function table command inhibit the command inhibit function prevents new commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram which is selected (cs is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode register is loaded via inputs a0-11. see mode register heading in the register de nition section. the load mode register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tmrd is met. truth table ? commands and dqm operation (note 1) name (function) cs# ras# cas# we# dqm addr i/os command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) ( 3) l l h h x bank/row x read (select bank and column, and start read burst) (4) l h l h l/h 8 bank/col x write (select bank and column, and start write burst) (4) l h l l l/h 8 bank/col valid burst terminate l h h l x x active precharge (deactivate row in bank or banks) ( 5) l l h l x code x auto refresh or self refresh (enter self refresh mode) (6, 7) l l l h x x x load mode register (2) l l l l x op-code x write enable/output enable (8) ? ? ? ? l ? active write inhibit/output high-z (8) ? ? ? ? h ? high-z notes: 1. cke is high for all commands shown except self refresh. 2. a0-11 de ne the op-code written to the mode register. 3. a0-12 provide row address, and ba0, ba1 determine which bank is made active. 4. a0-8 provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0, ba1 determine which bank is being read from or written to. 5. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks precharged and ba0, ba1 are ?don?t care.? 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. activates or deactivates the i/os during writes (zero-clock delay) and reads (two-clock delay).
wedpn16m64vr-xb2x 8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a12 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read data appears on the i/os subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the corresponding i/os will be high-z two clocks later; if the dqm signal was registered low, the i/os will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the i/os is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a speci ed time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature which performs the same individual-bank precharge function described above, without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a speci c read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst, except in the full-page burst mode, where auto precharge does not apply. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time (t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time. burst terminate the burst terminate command is used to truncate either xed-length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated. auto refresh auto refresh is used during normal operation of the sdram and is analagous to cas-before-ras (cbr) refresh in conventional drams. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. each 256mb sdram requires 8,192 auto refresh cycles every refresh period (tref). providing a distributed auto refresh command will meet the refresh requirement and ensure
wedpn16m64vr-xb2x 9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 that each row is refreshed. alternatively, 8,192 auto refresh commands can be issued in a burst at the minimum cycle rate (t rc ), once every refresh period (t ref ). self refresh* the self refresh command can be used to retain data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). once the self refresh command is registered, all the inputs to the sdram become ?don?t care,? with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram provides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an inde nite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (stable clock is de ned as a signal cycling within timing constraints specified for the clock pin) prior to cke going back high. once cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr , because time is required for the completion of any internal refresh in progress. upon exiting the self refresh mode, auto refresh commands must be issued as both self refresh and auto refresh utilize the row refresh counter. * self refresh available in commercial and industrial temperatures only.
wedpn16m64vr-xb2x 10 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 dc electrical characteristics and operating conditions (notes 1, 6) v cc = +3.3v 0.3v; -55c t a +125c parameter/condition symbol min max units supply voltage v cc 3 3.6 v input high voltage: logic 1; all inputs (21) v ih 2v cc + 0.3 v input low voltage: logic 0; all inputs (21) v il -0.3 0.8 v input leakage current: any input 0v v in v cc (all other pins not under test = 0v) i i -5 5 a output leakage current: i/os are disabled; 0v v out v cc i oz -5 5 a output high voltage (i out = -4ma) v oh 2.4 ? v output low voltage (i out = 4ma) v ol ? 0.4 v absolute maximum ratings parameter unit voltage on v cc , v ccq supply relative to v ss -1 to 4.6 v voltage on nc or i/o pins relative to v ss -1 to 4.6 v operating temperature t a (mil) -55 to +125 c operating temperature t a (ind) -40 to +85 c storage temperature, plastic -55 to +125 c note: stress greater than those listed under "absolute maximum ratings" may cause per ma nent damage to the device. this is a stress rating only and func tion al op er a tion of the device at these or any other conditions greater than those in di cat ed in the operational sections of this speci cation is not implied. exposure to ab so lute maximum rating con di tions for extended periods may affect reliability. capacitance (note 2) parameter symbol max unit input capacitance: clk c i1 14 pf addresses, ba0-1 input capacitance c a 7pf input capacitance: all other input-only pins c i2 8 pf input/output capacitance: i/os c io 8 pf register functions oe/le c reg 14 pf i dd specifications and conditions (notes 1,6,11,13) v cc = +3.3v 0.3v; -55c t a +125c parameter/condition symbol max units operating current: active mode; burst = 2; read or write; t rc = t rc (min); cas latency = 3 (3, 18, 19) i cc1 700 ma standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress (3, 12, 19) i cc3 240 ma operating current: burst mode; continuous burst; read or write; all banks active; cas latency = 3 (3, 18, 19) i cc4 750 ma self refresh current: cke 0.2v commercial and industrial temperatures only (27, 28) i cc7 10 ma bga thermal resistance description symbol max unit notes junction to ambient (no air ow) ja 16.8 c/w 1 junction to ball jb 12.2 c/w 1 junction to case (top) jc 6.5 c/w 1 note: refer to pbga thermal resistance correlation application note at www.whiteedc.com in the application notes section for modeling conditions.
wedpn16m64vr-xb2x 11 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 electrical characteristics and recommended ac operating characteristics (notes 5, 6, 8, 9, 11, 29) parameter symbol -133 -125 -100 unit min max min max min max access time from clk (pos. edge) cl = 3 t ac 5.4 5.8 6 ns cl = 2 t ac 666ns address hold time t ah 0.8 1 1 ns address setup time t as 1.5 2 2 ns clk high-level width t ch 2.5 3 3 ns clk low-level width t cl 2.5 3 3 ns clock cycle time (22) cl = 3 t ck 7.5 8 10 ns cl = 2 t ck 10 10 15 ns cke hold time t ckh 0.8 1 1 ns cke setup time t cks 1.5 2 2 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 1 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 2 2 ns data-in hold time t dh 0.8 1 1 ns data-in setup time t ds 1.5 2 2 ns data-out high-impedance time (10) cl = 3 (10) t hz 5.4 5.8 6 ns cl = 2 (10) t hz 66 6ns data-out low-impedance time t lz 11 1ns data-out hold time (load) t oh 33 3ns data-out hold time (no load) (26) t oh n 1.8 1.8 1.8 ns active to precharge command t ras 44 120,000 50 120,000 50 120,000 ns active to active command period t rc 66 70 70 ns active to read or write delay t rcd 20 20 20 ns refresh period (8,192 rows) ? commercial, industrial t ref 64 64 64 ms refresh period (8,192 rows) ? military t ref 16 16 16 ms auto refresh period t rfc 66 70 70 ns precharge command period t rp 20 20 20 ns active bank a to active bank b command t rrd 15 20 20 ns transition time (7) t t 0.3 1.2 0.3 1.2 0.3 1.2 ns write recovery time (23) t wr 1 clk + 7ns 1 clk + 7ns 1 clk + 7ns ? (24) 15 15 15 ns exit self refresh to active command t xsr 75 80 80 ns
wedpn16m64vr-xb2x 12 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 notes: 1. all voltages referenced to vss. 2. this parameter is not tested but guaranteed by design. f = 1 mhz, t a = 25c. 3. i dd is dependent on output loading and cycle rates. speci ed values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum speci cations are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. an initial pause of 100 s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v cc must be powered up simultaneously.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate speci cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5v with equivalent load: 10. t hz de nes the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. 12. other input signals are allowed to transition no more than once every two clocks and are otherwise at valid v ih or v il levels. 13. i cc speci cations are tested after the device is properly initialized. 14. timing actually speci ed by t cks ; clock(s) speci ed as a reference only at minimum cycle rate. 15. timing actually speci ed by t wr plus t rp ; clock(s) speci ed as a reference only at minimum cycle rate. 16. timing actually speci ed by t wr . 17. required clocks are speci ed by jedec functionality and are not dependent on any timing parameter. 18. the i cc current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 19. address transitions average one transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. v ih overshoot: v ih (max) = v cc + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width -3ns. 22. the clock frequency must remain constant (stable clock is de ned as a signal cycling within timing constraints speci ed for the clock pin) during access or precharge states (read, write, including t wr , and precharge commands). cke may be used to reduce the data rate. 23. auto precharge mode only. the precharge timing budget (t rp ) begins 7.5ns after the rst clock delay, after the last write is executed. 24. precharge mode only. 25. jedec and pc100 specify three clocks. 26. parameter guaranteed by design. 27. self refresh available in commercial and industrial temperatures only. 28. oe# high. 29. all ac timings do not count extra clock cycle needed on control signals to be registered. ac functional characteristics (notes 5,6,7,8,9,11,29) parameter/condition symbol -133 -125 -100 units read/write command to read/write command (17) t ccd 111t ck cke to clock disable or power-down entry mode (14) t cked 111 t ck cke to clock enable or power-down exit setup mode (14) t ped 111t ck dqm to input data delay (17) t dqd 000 t ck dqm to data mask during writes t dqm 000 t ck dqm to data high-impedance during reads t dqz 222 t ck write command to input data delay (17) t dwd 000 t ck data-in to active command (15) t dal 554t ck data-in to precharge command (16) t dpl 222 t ck last data-in to burst stop command (17) t bdl 1 1 1t ck last data-in to new read/write command (17) t cdl 111 t ck last data-in to precharge command (16) t rdl 222 t ck load mode register command to active or refresh command (25) t mrd 2 2 2t ck data-out to high-impedance from precharge command (17) cl = 3 t roh 333t ck cl = 2 t roh 222t ck
wedpn16m64vr-xb2x 13 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 package dimension ?b2?: 219 plastic ball grid array (pbga) all linear dimensions are millimeters and parenthetically in inches bottom view 12345678910111213141516 t r p n m l k j h g f e d c b a 219 x ? 0.762 (0.030) nom 1.27 (0.050) nom 25.1 (0.988) max 19.05 (0.750) nom 21.1 (0.831) max 19.05 (0.750) nom 2.03 (0.080) max 0.61 (0.024) nom
wedpn16m64vr-xb2x 14 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 ordering information wed p n 16m64 v r - xxx b2 x device grade: m = military -55c to +125c i = industrial -40c to +85c c =commercial 0c to +70c package: b2 = 219 plastic ball grid array (pbga), 25mm x 21mm frequency (mhz) 133 = 133mhz 125 = 125mhz 100 = 100mhz improvement mark r = registered 3.3v power supply configuration, 16 m x 64 sdram plastic white electronic designs corp.
wedpn16m64vr-xb2x 15 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs january 2005 rev. 0 document title 16m x 64 registered synchronous dram revision history rev # history release date status rev 0 initial release january 2005 final

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